FRAM (Ferroelectric Random Access Memory) is a type of non-volatile memory device that uses such a ferroelectric capacitor and preserves stored information even when the power is off. Additionally, the FRAM has high-speed access, less power consumption, and excellent shock-resistance. Accordingly, the FRAM would be expected to be used as a main storage device for various electronic devices and equipment, such as computers, networks and mobile devices.
In the FRAM, a memory cell is composed of the ferroelectric capacitor and a pass transistor, and which stores logical data “1” or “0” depending on polarization state of the ferroelectric capacitor. When a voltage is applied across the ferroelectric capacitor, a ferroelectric material is polarized according to the direction of an electric field. Hence, a threshold voltage at which a change in the polarization state of the ferroelectric material occurs is called a “coercive voltage”. In reading data stored in the memory cell, a voltage is applied between both electrodes of the ferroelectric capacitor to cause a potential difference, and accordingly excite charges on a bit line. The state of the data stored in the memory cell is sensed as a change in an amount of the charges excited on the bit line.
In FIG. 1, a circuit of the ferroelectric random access memory is illustrated, as a prior art, “A 0.25-um 3.0-V 1T1C 32-Mb Nonvolatile Ferroelectric RAM with Address Transition Detector and Current Forcing Sense Amplifier Scheme”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, November 2002, wherein a word line 111 is connected to memory cells 150 and 151, next word line 112 is connected to memory cells 152 and 153, and last word line 113 is connected to memory cells 154 and 155. The memory cell 150 is composed of the pass transistor 156 and the ferroelectric capacitor 157. And plate lines 121 and 122 are connected to the capacitor of the memory cells. As shown in the figure, a plurality of memory cells is connected to single bit line for integrating more memory cells on a chip, so that the bit line is long and heavily loaded. With heavily loaded bit line, capacitance value of the ferroelectric capacitor should be big enough to drive the bit line for reading. And access time is slow because there is a waiting time before the bit line is redistributed by the charges of the ferroelectric capacitor.
And a problem with the conventional one transistor-one capacitor FRAM is slow speed, because the plate line of the capacitor is driven by a plate line driver circuit from ground voltage to high voltage for reading and writing. For driving the plate line, a big driver circuit is required because the plate line is much heavier than that of bit line. Driving the plate line takes time and adding the driver circuit occupies more chip area. In order to force the plate line to a constant voltage, there are many prior arts as published, U.S. Pat. No. 5,416,735, “Non-volatile random access memory with ferroelectric capacitor”, U.S. Pat. No. 6,147,895, “Ferroelectric memory with two ferroelectric capacitors in memory cell and . . . ”, and U.S. Pat. No. 5,121,353, “Ferroelectric capacitor memory circuit MOS setting and transmission transistor”. However, the FRAM is not so fast, because other memories, such as DRAM and SRAM are still better than that of FRAM.
For improving the performance, hierarchical bit line architecture is applied as published, U.S. Pat. No. 7,382,641 “FeRAM for high speed sensing”, and U.S. Pat. No. 6,574,135 “Shared sense amplifier for ferroelectric memory cell”. Even though those hierarchical bit line architectures have been applied for improving the FRAM, the FRAM with the prior arts is not fast than SRAM, not denser than DRAM and not denser than flash memory.
In these respects, there is still a need in the art for improving the FRAM, because the FRAM is a good candidate for replacing the conventional semiconductor memory. In the present invention, new memory architecture is realized for focusing on replacing SRAM with a re-invented FRAM, which reduces area of the memory cell. And speed of the FRAM is close to that of the conventional SRAM with the new memory architecture and circuit.
And this application is a continuation of the U.S. patent application Ser. No. 12/253,997, filed on Oct. 19, 2008 and application Ser. No. 12/471,472, filed on May 26, 2009. In the present invention, the FRAM is renovated for realizing high speed and achieving area reduction by applying short bit line memory architecture, while most of the prior arts have tried to develop FRAM memory cell array structure with conventional circuits and architecture. And two 2T1C FRAM cells are used for storing a non-inverting data and an inverting data, which need not a reference voltage generator for sensing. And a local sense amp is used for reading the memory cell through a short local bit line pair, a global sense amp is connected to the local sense amp through a global bit line pair for receiving the read output, and a locking signal generator is used for locking or disabling the local sense amp after reading, which reduces a cycle time with quick write-back operation. More detailed description will followed as below.